1. Field of the Invention
This invention relates to a fine, high-performance dual gate field-effect transistor, and to a method of manufacturing the transistor.
2. Description of the Prior Art
As transistors become increasingly fine, it has given rise to a pronounced short channel effect in which fluctuations in gate length produce variations in threshold values. The use of a dual gate structure is known to be an optimum way of preventing the short channel effect (see Japanese Patent Publication Gazette No. 62-1270). However, as far as the present inventors know, no industrial method of fabricating a field-effect transistor with a dual gate structure has actually been proposed. In particular, no transistor has been proposed in which a group of an upper gate and a lower gate and another group of a source and a drain are self-aligning and the parasitic capacitance that hinders high-speed operation in a field-effect transistor is minimized, nor has a method of commercially producing such a transistor been proposed.
The reason for this is that in the prior art procedure used to fabricate a MOS transistor, a gate is fabricated in a first photolithography step and a source and a drain are formed using the gate as a mask so that the source and drain self-aligns with the gate. That is, the fact that there is no planar overlay between the gate and the source and between the gate and the drain is utilized.
However, when the gate comprises an upper and a lower gate, it is difficult to form the two gates so that they self-align. If, for example, the upper gate is formed first by the photolithography step, it is difficult to then form the lower gate, a source and a drain so that they align with the upper gate. This is because while one group of the upper and lower gates has to be formed as a planar overlay, another group of the source and drain has to be formed so that the another group does not overlay the one group, hence there is the difficulty in trying to use a single process to form both groups. Because of this difficulty, dual gate field-effect transistors are usually formed using two or more photolithography steps. However, the drawback with using two or more process steps is that the devices are more likely to be defective owing to errors in mask alignment.
This invention was accomplished to overcome the foregoing problems and has as an object to provide a fine, high-performance, self-aligning, dual gate field-effect transistor, and a method of commercially manufacturing the transistor.